MAX77874 datasheet(21/37 Pages) MAXIM

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25Ω). When the buck is enabled, the discharge resistors

are automatically disconnected regardless the state of the

BUCK0ADEN bit. Therefore, if active discharge is always

desired, the bit can be left enabled (logic 1) without caus-

ing additional loading when the buck is enabled.

Full Shutdown

By default, when the buck regulator is disabled, its bias

circuits are also disabled to save supply current. When

enabling the buck regulator, the bias is automatically

enabled and disabled. If faster startup is desired, the bias

circuits can be pre-enabled by setting the BIASEN bit

in the BUCK0CNFG0 register to logic 1. This comes at

the expense of higher supply current when the buck is

disabled.

Even when the regulator and the bias are disabled, top-

level circuits in the MAX77874 are still alive. The I2C is

active and registers can still be read from and written

to. Setting VIO = 0V turns off the top-level circuits and

results in the lowest possible shutdown current at VIN.

Additionally, when VIO = 0V, all registers are reset to their

default values.

See the Typical Operating Characteristics for a graph of

supply current in each operating mode, as well as a scope

photo of the faster startup.

Output Voltage Selection

The output voltage is I2C programmable from 0.25V to

1.3V in 5mV steps using the I2C_SD0_VOUT[7:0] bits in

the I2C_SD0_VOUT configuration register. The default

setting is trimmed to 0x82 = 0.900V. Consult the factory

if a different default setting is required. This setting is

programmable with the quad phase core buck enabled

or disabled.

Dynamic Voltage Scaling (DVS)

The quad phase core buck includes DVS functionality.

The DVS output voltage is I2C programmable from 0.25V

to 1.3V in 5mV steps using the VBUCKDVS[7:0] bits in

the VBUCKDVS configuration register. The default setting

is trimmed to 0x82 = 0.900V. Consult the factory if a differ-

ent default setting is required. The setting is programma-

ble with the quad phase core buck enabled or disabled.

DVS Functionality

The purpose of the DVS function is to allow the buck

output voltage to quickly change from one output voltage

to another. An I2C write of a register can take several

microseconds to a few milliseconds to complete depend-

ing upon the I2C speed. The I2C_SDOUT_VOUT[7:0]

pin is low. When the DVS pin is high, the buck output

voltage is controlled by the VBUCKDVS[7:0] register. See

Figure 1. When the I2C_SDOUT_VOUT register is set at

a higher voltage than the VBUCKDVS register and the

DVS pin transitions from low to high, then the buck output

voltage falls to the voltage set by the VBUCKDVS register

at a slew rate specified by the BUCK0FSR[1:0] bits in the

BUCK0CNFG1 register. When the DVS pin transitions

back from high to low, then the buck output voltage rises

to the value specified by the I2C_SDOUT_VOUT register

at a slew rate specified by the BUCK0RSR[1:0] bits in the

BUCK0CNFG1 register.

Figure 1. DVS Functionality

VOLTAGE SPECIFIED BY

I2C_SDOUT_VOUT

FALL SLEW RATE

SPECIFIED BY

BUCK0FSR

VOLTAGE SPECIFIED BY

VBUCKDVS REGISTER

RISE SLEW RATE

SPECIFIED BY

BUCK0RSR

BUCK OUTPUT

VOLTAGE

DVS PIN

MAX77874

16A High-Performance Quad-Phase Buck Regulator

for Multicore CPU and GPU Processors

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