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MCP47FVB21 Datasheet(PDF) 18 Page - Microchip Technology

Part # MCP47FVB21
Description  8- /10- /12-Bit Single/Dual Voltage Output Volatile Digital-to-Analog Converters with I짼C??Interface
PDF  92 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP47FVB21 Datasheet(HTML) 18 Page - Microchip Technology

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MCP47FVBXX
DS20005405A-page 18
 2015 Microchip Technology Inc.
1.2
I2C Mode Timing Waveforms and Requirements
FIGURE 1-2:
Power-on and Brown-out Reset Waveforms.
FIGURE 1-3:
I2C™ Power-Down Command Timing.
TABLE 1-2:
RESET TIMING
Timing Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C
 TA  +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +1.8V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
Power-on Reset
Delay
tPORD
60
µs
Monitor ACK bit response to ensure device responds to
command.
Brown-out Reset
Delay
tBORD
—45
µs
VDD transitions from VDD(MIN)  > VPOR
VOUT driven to VOUT disabled
Power-Down Output
Disable Time Delay
TPDD
10.5
µs
PDxB:PDxA = ‘11’, ‘10’, or ‘01’ -> “00” started from fall-
ing edge of the SCL at the end of the 8th clock cycle.
Volatile DAC register = FFh, VOUT =10mV. VOUT not
connected.
Power-Down Output
Enable Time Delay
TPDE
1
µs
PDxB:PDxA = “00”
 ‘11’, ‘10’, or ‘01’ started from
falling edge of the SCL at the end of the 8th clock cycle.
VOUT = VOUT - 10 mV. VOUT not connected.
VDD
SDA
tPORD
tBORD
VOUT
SCL
VIH
VIH
VPOR (VBOR)
VOUT at High Z
I2C™ Interface is operational
SDA
SCL
ACK
Stop
Start
ACK
VOUT
tPDE
tPDD



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