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MCP48FVB21 Datasheet(PDF) 32 Page - Microchip Technology |
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MCP48FVB21 Datasheet(HTML) 32 Page - Microchip Technology |
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32 / 84 page  MCP48FVBXX DS20005466A-page 32 2015 Microchip Technology Inc. 4.2.2 DEVICE CONFIGURATION MEMORY The STATUS register is described in Register 4-4. 4.2.3 UNIMPLEMENTED REGISTER BITS Read commands of a valid location will read unimplemented bits as ‘0’. 4.2.4 UNIMPLEMENTED (RESERVED) LOCATIONS Normal (voltage) commands (read or write) to any unimplemented memory address (reserved) will result in a command error condition (CMDERR). Read commands of a reserved location will read bits as ‘1’. 4.2.4.1 Default Factory POR Memory State Table 4-2 shows the default factory POR initialization of the device memory map for the 8-, 10- and 12-bit devices. TABLE 4-2: FACTORY DEFAULT POR / BOR VALUES Function POR/BOR Value Function POR/BOR Value 00h Volatile DAC0 Register 7Fh 1FFh 7FFh 10h Reserved (1, 2) FFh 3FFh FFFh 01h Volatile DAC1 Register 7Fh 1FFh 7FFh 11h Reserved (1, 2) FFh 3FFh FFFh 02h Reserved (1) FFh 3FFh FFFh 12h Reserved (1, 2) FFh 3FFh FFFh 03h Reserved (1) FFh 3FFh FFFh 13h Reserved (1, 2) FFh 3FFh FFFh 04h Reserved (1) FFh 3FFh FFFh 14h Reserved (1, 2) FFh 3FFh FFFh 05h Reserved (1) FFh 3FFh FFFh 15h Reserved (1, 2) FFh 3FFh FFFh 06h Reserved (1) FFh 3FFh FFFh 16h Reserved (1, 2) FFh 3FFh FFFh 07h Reserved (1) FFh 3FFh FFFh 17h Reserved (1, 2) FFh 3FFh FFFh 08h VREF Register 0000h 0000h 0000h 18h Reserved (1, 2) FFh 3FFh FFFh 09h Power-Down Register 0000h 0000h 0000h 19h Reserved (1, 2) FFh 3FFh FFFh 0Ah Gain and Status Register 0080h 0080h 0080h 1Ah Reserved (1, 2) FFh 3FFh FFFh 0Bh Reserved (1) FFh 3FFh FFFh 1Bh Reserved (1, 2) FFh 3FFh FFFh 0Ch Reserved (1) FFh 3FFh FFFh 1Ch Reserved (1, 2) FFh 3FFh FFFh 0Dh Reserved (1) FFh 3FFh FFFh 1Dh Reserved (1, 2) FFh 3FFh FFFh 0Eh Reserved (1) FFh 3FFh FFFh 1Eh Reserved (1, 2) FFh 3FFh FFFh 0Fh Reserved (1) FFh 3FFh FFFh 1Fh Reserved (1, 2) FFh 3FFh FFFh Volatile Memory address range Nonvolatile Memory address range Note 1: Reading a reserved memory location will result in the SPI command Command Error condition. The SDO pin will output all ‘0’s. Forcing the CS pin to the VIH state will reset the SPI interface. 2: Nonvolatile memory address range is shown to reflect memory map compatibility with the MCP48FEBXX family of devices. |
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