INA237 datasheet(27/48 Pages) TI

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Table 7-13. DIAG_ALRT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

SLOWALERT

R/W

When enabled, ALERT function is asserted on the completed

averaged value.

This gives the flexibility to delay the ALERT until after the averaged

value.

0h = ALERT comparison on non-averaged (ADC) value

1h = ALERT comparison on averaged value

APOL

R/W

Alert Polarity bit sets the Alert pin polarity.

0h = Normal (Active-low, open-drain)

1h = Inverted (active-high, open-drain )

11-10

RESERVED

Reserved. Always read 0.

MATHOF

This bit is set to 1 if an arithmetic operation resulted in an overflow

error.

It indicates that current and power data may be invalid.

0h = Normal

1h = Overflow

Must be manually cleared by triggering another conversion.

RESERVED

Reserved. Always read 0.

TMPOL

R/W

This bit is set to 1 if the temperature measurement exceeds the

threshold limit in the temperature over-limit register.

0h = Normal

1h = Over Temp Event

When ALATCH =1 this bit is cleared by reading this register.

SHNTOL

R/W

This bit is set to 1 if the shunt voltage measurement exceeds the

threshold limit in the shunt over-limit register.

0h = Normal

1h = Over Shunt Voltage Event

When ALATCH =1 this bit is cleared by reading this register.

SHNTUL

R/W

This bit is set to 1 if the shunt voltage measurement falls below the

threshold limit in the shunt under-limit register.

0h = Normal

1h = Under Shunt Voltage Event

When ALATCH =1 this bit is cleared by reading this register.

BUSOL

R/W

This bit is set to 1 if the bus voltage measurement exceeds the

threshold limit in the bus over-limit register.

0h = Normal

1h = Bus Over-Limit Event

When ALATCH =1 this bit is cleared by reading this register.

BUSUL

R/W

This bit is set to 1 if the bus voltage measurement falls below the

threshold limit in the bus under-limit register.

0h = Normal

1h = Bus Under-Limit Event

When ALATCH =1 this bit is cleared by reading this register.

POL

R/W

This bit is set to 1 if the power measurement exceeds the threshold

limit in the power limit register.

0h = Normal

1h = Power Over-Limit Event

When ALATCH =1 this bit is cleared by reading this register.

CNVRF

R/W

This bit is set to 1 if the conversion is completed.

0h = Normal

1h = Conversion is complete

When ALATCH =1 this bit is cleared by reading this register or

starting a new triggered conversion.

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INA237-Q1

SBOSA27A – JUNE 2020 – REVISED JUNE 2021

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