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ACE25QA200GFMLTH Datasheet(PDF) 6 Page - ACE Technology Co., LTD.

Part # ACE25QA200GFMLTH
Description  2M BIT SPI NOR FLASH
PDF  30 Pages
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Manufacturer  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25QA200GFMLTH Datasheet(HTML) 6 Page - ACE Technology Co., LTD.

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ACE25QA200G
2M BIT SPI NOR FLASH
VER 1.2
6
(D)
Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any instruction
sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to
follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal
Write cycle in progress).
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes
ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the
device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
Status Register
Table 3. Status Register
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Reserved
Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase instructions. These bits are written with the Write Status Register
instruction. When the Block Protect (BP2, BP1, and BP0) bits are set to 1, the relevant memory area.
Becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect
(BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.



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