Electronic Components Datasheet Search
  English  ▼

X  

DM7495N Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DM7495N
Description  4-Bit Parallel Access Shift Registers
PDF  6 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM7495N Datasheet(HTML) 3 Page - National Semiconductor (TI)

  DM7495N Datasheet HTML 1Page - National Semiconductor (TI) DM7495N Datasheet HTML 2Page - National Semiconductor (TI) DM7495N Datasheet HTML 3Page - National Semiconductor (TI) DM7495N Datasheet HTML 4Page - National Semiconductor (TI) DM7495N Datasheet HTML 5Page - National Semiconductor (TI) DM7495N Datasheet HTML 6Page - National Semiconductor (TI)  
Zoom Inzoom in Zoom Outzoom out
 3 / 6 page
background image
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
RL e 400X CL e 15 pF
Units
To (Output)
Min
Max
fMAX
Maximum Clock Frequency
25
MHz
tPHL
Propagation Delay Time
Clock to
35
ns
High to Low Level Output
Output
tPLH
Propagation Delay Time
Clock to
35
ns
Low to High Level Output
Output
Function Table
Inputs
Outputs
Mode
Clocks
Serial
Parallel
QA
QB
QC
QD
Control
2(L)
1(R)
A
B
C
D
HH
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
v
XXa
b
c
d
a
b
c
d
H
v
XX
QB
QC
QD
dQBn
QCn
QDn
d
LL
H
X
X
X
X
X
QA0
QB0
QC0
QD0
LX
v
HX
X
X
X
H
QAn
QBn
QCn
LX
v
LX
X
X
X
L
QAn
QBn
QCn
u
LL
X
X
X
X
X
QA0
QB0
QC0
QD0
v
LL
X
X
X
X
X
QA0
QB0
QC0
QD0
v
LH
X
X
X
X
X
QA0
QB0
QC0
QD0
u
HL
X
X
X
X
X
QA0
QB0
QC0
QD0
u
HH
X
X
X
X
X
QA0
QB0
QC0
QD0
Shifting left requires external connection of QB to A QC to B QD to C Serial data is entered at input D
H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care (Any input including transitions)
v e Transition from high to low level u e Transition from low to high level
a b c d e The level of steady state input at inputs A B C or D respectively
QA0 QB0 QC0 QD0 e The level of QA QB QC QD respectively before the indicated steady state input conditions were established
QAn QBn QCn QDn e The level of QA QB QC QD respectively before the most recent
v transition of the clock
Logic Diagram
TLF6534 – 2
3



Html Pages

1 2 3 4 5 6


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com