OR3C80 datasheet(97/210 Pages) AGERE

97 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

FPGA Configuration Modes (continued)

Slave Serial Mode

The slave serial mode is primarily used when multiple

FPGAs are configured in a daisy-chain (see the Daisy-

Chaining section). It is also used on the FPGA evalua-

tion board that interfaces to the download cable. A

device in the slave serial mode can be used as the lead

device in a daisy-chain. Figure 61 shows the connec-

tions for the slave serial configuration mode.

The configuration data is provided into the FPGA’s DIN

input synchronous with the configuration clock CCLK

input. After the FPGA has loaded its configuration data,

it retransmits the incoming configuration data on

DOUT. CCLK is routed into all slave serial mode

devices in parallel.

Multiple slave FPGAs can be loaded with identical con-

figurations simultaneously. This is done by loading the

configuration data into the DIN inputs in parallel.

5-4485(F)

Figure 61. Slave Serial Configuration Schematic

Slave Parallel Mode

The slave parallel mode is essentially the same as the

slave serial mode except that 8 bits of data are input on

pins D[7:0] for each CCLK cycle. Due to 8 bits of data

being input per CCLK cycle, the DOUT pin does not

contain a valid bit stream for slave parallel mode. As a

result, the lead device cannot be used in the slave

parallel mode in a daisy-chain configuration.

Figure 62 is a schematic of the connections for the

slave parallel configuration mode. WR and CS0 are

active-low chip select signals, and CS1 is an active-

high chip select signal. These chip selects allow the

user to configure multiple FPGAs in slave parallel

mode using an 8-bit data bus common to all of the

FPGAs. These chip selects can then be used to select

the FPGA(s) to be configured with a given bit stream.

The chip selects must be active for each valid CCLK

cycle until the device has been completely pro-

grammed. They can be inactive between cycles but

must meet the setup and hold times for each valid pos-

itive CCLK. D[7:0] of the FPGA can be connected to

D[7:0] of the microprocessor only if a standard prom

file format is used. If a .bit or .rbt file is used from

ORCA Foundry, then the user must mirror the bytes in

the .bit or .rbt file OR leave the .bit or .rbt file

unchanged and connect D[7:0] of the FPGA to D[0:7]

of the microprocessor.

5-4487(F)

Figure 62. Slave Parallel Configuration Schematic

MICRO-

PROCESSOR

DOWNLOAD

CABLE

HDC

SERIES

FPGA

LDC

VDD

CCLK

PRGM

DOUT

TO DAISY-

CHAINED

DEVICES

DONE

DIN

INIT

ORCA

MICRO-

PROCESSOR

SYSTEM

D[7:0]

DONE

CCLK

CS1

HDC

LDC

VDD

INIT

PRGM

CS0

SERIES

FPGA

ORCA

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