SH7750 datasheet(13/1039 Pages) RENESAS

13 / 1039 page

Rev. 6.0, 07/02, page xi of I

Section

Page

Item

Description

13.2.8 Memory Control

355

Bits 15 to 13—Write

Precharge Delay (TRWL2–

TRWL0)

Description added

358

For Synchronous DRAM

Interface

AMX6 description and

Notes amended

13.2.10 Synchronous DRAM

Mode Register (SDMR)

362 to

364

Description amended,

and Note added

370

Description amended

13.3.1 Endian/Access Size

and Data Alignment

371

Data Configuration

Quadword partially

amended

13.3.2 Areas

382

Area 0, Area 1

Description added and

amended

13.3.3 SRAM Interface

387

Basic interface changed

to SRAM interface

387

Basic Timing

Description amended

388, 393

to 395

Figures 13.6, 13.11 to 13.13

Notes added

395

Read-Strobe Negate Timing

(Setting Only Possible in the

SH7750R)

Description added and

amended

13.3.4 DRAM Interface

400 to 408 Figures 13.17 to 13.22

Notes added

13.3.5 Synchronous DRAM

Interface

413

Connection of Synchronous

DRAM

Description added

415

Address Multiplexing

Description amended

417 to

428

Figure 13.28 to 13.37

Note added

435

Power-On Sequence

Newly added

438

Notes on Changing the Burst

Length (Variation Only

Possible in the SH7750R)

Newly added

440

Connecting a 128-Mbit/256-

Mbit Synchronous DRAM with

64-bit Bus Width

Newly added

13.3.6 Burst ROM Interface

441, 442

Description amended

442 to 444 Figure 13.46 to 13.48

Notes added

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