ADA4255ACPZ-R7 datasheet(28/64 Pages) AD

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Data Sheet

ADA4255

THEORY OF OPERATION

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Rev. 0 | 28 of 64

POWER SUPPLIES

The ADA4255 requires that three low voltages supplies be pow-

ered: the low voltage charge pump supply (VDDCP), the low

voltage analog output amplifier supply (AVDD), and the low voltage

digital supply (DVDD).

The low voltage charge pump supply is used internally to generate

high voltage, bipolar supplies VDDH and VSSH, which power the

input amplifier of the ADA4255. On-chip high voltage supply gener-

ation allows the ADA4255 to be isolated using only low voltage

components while maintaining high voltage, high impedance input

operation. The equations for typical VDDH and VSSH are as

follows:

VDDH = 4.65 × VDDCP − 0.9 V

VSSH = -4.65 × VDDCP + 1.6 V

VDDH and VSSH are output to pins so that the required external

decoupling capacitance can be applied. This decoupling is not

optional and is required to stabilize VDDH and VSSH. Figure 90

shows the minimum recommended 10 μF and 0.1 μF decoupling

capacitors connected to VDDH and VSSH. Up to 500 μA of addi-

tional load current can be sourced by VDDH or sunk by VSSH with

the charge pump clock at its default of 16 MHz. The charge pump

frequency can be reduced to 8 MHz, which results in lower current

consumption on VDDCP.

VSSH is connected to the substrate of the ADA4255. Therefore,

VSSH must be connected to the most negative supply voltage in

the circuit, and VSSH must not exceed AVSS. It is recommended

to use a Schottky diode to clamp VSSH to AVSS. The Schottky

diode must have a forward bias voltage of 0.3 V or lower at 1 mA

and withstand −28 V of reverse voltage. The ADA4255 monitors the

VDDH and VSSH supplies to detect if the VDDH or VSSH drops

below 8 V and sets the POR_HV flag.

The low voltage analog output amplifier supply, AVDD and AVSS,

powers the output amplifier of the ADA4255. AVSS must be within

VSSH − 0.3 V to VSSH + 30 V and VDDH – 30 V to VDDH + 0.3 V.

AVDD − AVSS is typically a 5 V single supply, compatible with most

high precision ADCs. Use 0.1 μF and 10 μF decoupling capacitors

between AVDD and AVSS as close as possible to the AVDD and

AVSS supply pins.

The digital supplies, DVDD and DVSS, power the digital circuitry

inside the ADA4255. DVSS must be the same potential as AVSS.

Use 0.1 μF and 10 μF decoupling capacitors from DVDD to DVSS

as close as possible to the DVDD and DVSS supply pins. Figure 90

shows a typical ADA4255 supply configuration. The recommended

decoupling values described in this section are minimum recom-

mendations. Depending on amplifier loading and system noise,

higher capacitance values and/or additional lower capacitor values

may improve performance.

Figure 90. Typical ADA4255 Power Supply Configuration

ESD MAP

Figure 91 shows the various ESD diode paths inside the ADA4255.

Figure 91, in conjunction with the Absolute Maximum Ratings

section, helps in understanding current paths during power-on and

fault conditions.

Figure 91. ESD Map

ADA4255ACPZ-R7 Datasheet(PDF) 28 Page - Analog Devices

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