FXLS8974CF datasheet(13/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

[3]

tVD;DAT referred to the time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[4]

The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode respectively, but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time.

[5]

tVD;ACK = time for ACK signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[6]

A Fast-mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. Also the acknowledge timing

must meet this set-up time.

[7]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. The

maximum fall time allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

the maximum specified tf.

[8]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this

specified fall time when considering bus timing.

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70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

SDA

SCL

9th clock

1st clock cycle

9th clock

1 / fSCL

tLOW

tSET

tSU:DAT

tSU:STA

tHD:STA

tSU:STO

tVD:ACK

tBUF

tSP

tHIGH

tVD:DAT

tHD:DAT

continued

Figure 4. I2C secondary timing diagram for Standard-mode, Fast-mode and Fast-mode Plus

12.1.1 General I2C operation

There are two signals associated with the I2C-bus: the Serial Clock Line (SCL) and the

Serial Data line (SDA). SDA is a bidirectional signal used for sending and receiving the

data to/from the interface. External pull-up resistors connected to VDD are required for

SDA and SCL. When the I2C-bus is free, SCL and SDA are high.

The maximum practical operating frequency for I2C in a given system implementation

depends on several factors including the pull-up resistor and voltage values and total bus

capacitance (PCB trace + parasitic device capacitances).

The primary starts a transaction on the bus through a start condition (ST) signal, which

is defined as a HIGH-to-LOW transition on SDA line while the SCL line is held HIGH.

After the primary transmits the ST signal, the bus is considered busy. The next byte of

data transmitted contains the secondary address in the first seven bits, and the eighth bit,

the read/write bit, indicates whether the primary is receiving data from the secondary or

transmitting data to the secondary. When an address is sent, each device in the system

compares the first seven bits after the ST condition with its own address. If they match,

the device considers itself addressed by the primary. The ninth clock pulse, following the

secondary address byte (and each subsequent byte) is the acknowledge (ACK). The

transmitter must release the SDA line during the ACK period. The receiver must then pull

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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