13

3495B–DFLSH–8/05

AT26DF041

10. Input Test Waveforms and Measurement Levels

t

11. Output Test Load

12. AC Waveforms

Two different timing diagrams are shown below. Waveform 1 shows timing that is compatible

with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. The setup

and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.

Figure 12-1. Waveform 1 – SPI Mode 0

Figure 12-2. Waveform 2 – SPI Mode 3

AC

DRIVING

LEVELS

AC

MEASUREMENT

LEVEL

0.45V

2.0

0.8

2.4V

DEVICE

UNDER

TEST

30 pF

CS

SCK

SI

SO

VALID IN

tH

HIGH IMPEDANCE

VALID OUT

HIGH IMPEDANCE

CS

SCK

SI

SO

VALID IN

HIGH Z

VALID OUT

HIGH IMPEDANCE