Figure 8-2. Random Read

SCL

SDA

Start Condition

by Host

Device Address Byte

First Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

A

2

A

1

A16 0

0

Dummy Write

Start Condition

by Host

Device Address Byte

Data Word (n)

Stop Condition

by Host

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

A

2

A

1

A

0

1

0 D7 D6 D5 D4 D3 D2 D1 D0 1

A14 A13 A12 A11 A10 A9 A8

0

ACK

from Client

ACK

from Client

ACK

from Client

NACK

from Host

Second Word Address Byte

MSb

A7 A6 A5 A4

A3 A2

A1 A0

0

ACK

from Client

A15

8.3

Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus host receives a data

word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the

word address and serially clock out sequential data words. When the maximum memory address is reached, the data

word address will rollover and the sequential read will continue from the beginning of the memory array. All types of

read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start

condition to begin the next sequence.

Figure 8-3. Sequential Read

SCL

SDA

Start

by

Host

ACK

from

Client

ACK

from

Host

Device Address Byte

Data Word (n)

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

1

0

D7 D6

D5 D4 D3

D2 D1 D0

0

ACK

from

Host

NACK

from

Host

Stop

by

Host

ACK

from

Host

Data Word (n+1)

Data Word (n+2)

Data Word (n+x)

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

D7 D6 D5 D4 D3 D2

D1 D0

0 D7 D6 D5 D4 D3 D2 D1 D0 0

D7 D6 D5 D4 D3 D2 D1 D0

1

MSb

MSb

MSb

AT24CM02

Read Operations

Datasheet

DS20006197C-page 22