THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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TIMING AND SIGNAL DESCRIPTION OF THE THS1007

The reading from the THS1007 and writing to the THS1007 is performed by using the chip select inputs (CS0,

CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input

(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal

(R/W). The two chip select inputs can be used to interface easily to a processor.

combination of the external signals CS0, CS1 and RD (see Figure 33). This signal is then used to strobe the

words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes

of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and

RD

WR

Control/Data

Registers

CS0

CS1

RD

WR

Data Bits

Figure 33. Logical Combination of CS0, CS1, RD, and WR