THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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DETAILED DESCRIPTION

Reference Voltage

The THS1007 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V

and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP

and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish

the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

Analog Inputs

The THS1007 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected

individually and configured as single-ended or differential inputs. The desired analog input channel can be

programmed.

Converter

The THS1007 uses a 10-bit pipelined multistaged architecture, which achieves a high sample rate with low

power consumption. The THS1007 distributes the conversion over several smaller ADC sub-blocks, refining

the conversion with progressively higher accuracy as the device passes the results from stage to stage. This

distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.

A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input

sample while the second through the eighth stages operate on the seven preceding samples.

Conversion Clock

An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new

conversion is started with every falling edge of the applied clock signal. The conversion values are available

at the output with a latency of 5 clock cycles.

SYNC

In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK

after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1007.

Sampling Rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels.

Table 1 shows the maximum conversion rate for different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

CHANNEL CONFIGURATION

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

1 single-ended channel

1

6 MSPS

2 single-ended channels

2

3 MSPS

3 single-ended channels

3

2 MSPS

4 single-ended channels

4

1.5 MSPS

1 differential channel

1

6 MSPS

2 differential channels

2

3 MSPS

1 single-ended and 1 differential channel

2

3 MSPS

2 single-ended and 1 differential channels

3

2 MSPS

The maximum conversion rate per channel, fc, is given by:

fc

+ 6 MSPS

# channels