Reference Voltage

The MAX1181 requires an input voltage reference at its

REFIN pin to set the full-scale analog signal voltage

input. The ADC has a stable on-chip voltage reference of

2.048V that can be accessed at REFOUT. The EV kit was

designed to use the on-chip voltage reference by con-

necting REFIN to REFOUT through resistor R20. The user

can externally adjust the reference level, and hence the

full-scale range, by installing a resistor at the R19 pad.

The adjusted reference level can be calculated by

applying the following equation:

where R19 is the value of the resistor installed, R20 is a

10k

user can apply a stable, low noise, external voltage ref-

erence directly at the REFIN pad to set the full scale.

Output Signal

The MAX1181 features two 10-bit, parallel, CMOS-com-

patible, digital outputs channels (Channels A and B).

The digital output coding can be chosen to be either in

two’s complement format or straight offset binary format

by configuring jumper JU5. Refer to Table 3 for jumper

configuration. Two drivers buffer the ADC’s Channel A

and B digital outputs. The buffer is able to drive large

capacitive loads, which may be present at the logic

analyzer connection, without compromising the digital

output signal. The outputs of the buffers are connected

to a 50-pin header (J1) located on the right side of the

EV kit, where the user can connect a logic analyzer or

data-acquisition system. Refer to Table 4 for channel

and bit location on header J1.

V

R

RR

V

REFIN

REFOUT

=

+









×

19

19

20

MAX1181 Evaluation Kit

_______________________________________________________________________________________

5

JUMPER

SHUNT STATUS

PIN CONNECTION

EV KIT OPERATION

1 and 2

T/B connected to VDDUT

Digital output in two's complement

JU5

2 and 3

T/B connected to DGND

Digital output in straight offset binary

Table 3. Output Format

CHANNEL

A/B

STATE

BIT D0

BIT D1

BIT D2

BIT D3

BIT D4

BIT D5

BIT D6

BIT D7

BIT D8

BIT D9

NONMULTIPLEXED OUTPUT OPERATION

A

CLK

↑

N/A

J1-19

A0

J1-17

A1

J1-15

A2

J1-13

A3

J1-11

A4

J1-9

A5

J1-7

A6

J1-5

A7

J1-3

A8

J1-1

A9

B

CLK

↑

N/A

J1-23

B0

J1-25

B1

J1-27

B2

J1-29

B3

J1-31

B4

J1-33

B5

J1-35

B6

J1-37

B7

J1-39

B8

J1-41

B9

MULTIPLEXED OUTPUT OPERATION*

A

CLK

↓

J1-23

1

J1-19

A0

J1-17

A1

J1-15

A2

J1-13

A3

J1-11

A4

J1-9

A5

J1-7

A6

J1-5

A7

J1-3

A8

J1-1

A9

B

CLK

↑

J1-23

0

J1-19

A0

J1-17

A1

J1-15

A2

J1-13

A3

J1-11

A4

J1-9

A5

J1-7

A6

J1-5

A7

J1-3

A8

J1-1

A9

Table 4. Output Bit Location (Nonmultiplexed/Multiplexed Output Operation)

*For multiplexed output operation, Channel A and Channel B data is captured with a single 10-bit bus. Leave header designators

J25 (B1) through J41 (B9) open.