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PLL103-04SC Datasheet(PDF) 3 Page - PhaseLink Corporation

Part # PLL103-04SC
Description  1-to-4 Clock Distribution Buffer
PDF  4 Pages
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL103-04SC Datasheet(HTML) 3 Page - PhaseLink Corporation

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Preliminary
PLL103-04
1-to-4 Clock Distribution Buffer
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/26/00 Page 3
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VCC
-0.5
7
V
Input Voltage Range
VI
-0.5
VCC
+0.5
V
Output Voltage Range
VO
-0.5
VCC
+0.5
V
Soldering Temperature
260
°C
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature
0
70
°C
ESD Voltage
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Electrical Characteristics
VDD = 3.0~3.6V, unless otherwise stated
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input Low Current
IIL
VIN = 0V
19
50.0
µA
Input High Current
IIH
VIN = VDD
0.10
100.0
µA
Output Low Current
IOL
VOL = 1.5 V
50
mA
Output High Current
IOH
VOH = 1.5 V
50
mA
Power Down Supply Current
IDD
REF = 0MHz
0.3
50.0
µA
Supply Current
IDD
Unloaded outputs at 75MHz,
SEL inputs at VDD or GND
30.0
40.0
mA
3. TIMING CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Rise Time
Tr
Measured at 0.8V ~ 2.0V @ 3.3V
0.8
0.95
1.1
ns
Fall Time
Tf
Measured at 2.0V ~ 0.8V @ 3.3V
0.78
0.85
0.9
ns
Propagation
TPROP
VT = 1.5 V
1
4
6
ns
Output Duty Cycle
DT
45
50
55
%
Output-to-Output skew
Tskew
Rising edges at VDD/2
250
ps



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