PLL103-11

Low Skew Buffers

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 11/07/00 Page 4

2. BYTE 1: SDRAM(6:11) Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

27

1

SDRAM11 (Active/Inactive)

Bit 6

26

1

SDRAM10 (Active/Inactive)

Bit 5

23

1

SDRAM9 (Active/Inactive)

Bit 4

22

1

SDRAM8 (Active/Inactive)

Bit 3

-

1

Reserved

Bit 2

-

1

Reserved

Bit 1

19

1

SDRAM7 (Active/Inactive)

Bit 0

18

1

SDRAM6 (Active/Inactive)

3. BYTE 2: SDRAM12 Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

-

1

Reserved

Bit 6

12

1

SDRAM12 (Active/Inactive)

Bit 5

-

1

Reserved

Bit 4

-

1

Reserved

Bit 3

-

1

Reserved

Bit 2

-

1

Reserved

Bit 1

-

1

Reserved

Bit 0

-

1

Reserved