Preliminary

PLL602-89T

12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Low jitter XO for the 12MHz to 27MHz range.

• Integrated crystal load capacitor: no external

load capacitor required.

• 3 pairs of LVDS outputs and 1 CMOS output.

• 12-27 MHz fundamental crystal input.

• Low jitter (RMS): 2.5 ps period jitter (1 sigma).

• 2.5V to 3.3V operation.

• Available in 16-Pin SSOP package.

PIN CONFIGURATION

(Top View)

DESCRIPTION

The PLL602-89T is a high performance multiple output XO IC chip. It provides 3 pairs of LVDS and 1 CMOS out-

puts. The chip combines a crystal oscillator (XO) with a multiple-output buffer. It accepts a low cost fundamental

parallel resonant mode crystal from 12MHz to 27MHz, which is reproduced at the outputs. The very low jitter (2.5

ps RMS period jitter) makes this chip ideal for data and telecommunication applications.

BLOCK DIAGRAM

1

2

3

4

5

6

7

8

VDDBUF

9

10

11

12

13

14

15

16

VDDANA

VDDANA

XOUT

XIN

GNDBUF

GNDANA

CMOS_CLK

LVDS1BAR_CLK

LVDS1_CLK

GNDBUF

LVDS2BAR_CLK

LVDS2_CLK

VDDBUF

LVDS3BAR_CLK

LVDS3_CLK

XOUT

LVDS2_CLK

XIN

Oscillator

Amplifier

CMOS_CLK

LVDS2BAR_CLK

LVDS3_CLK

LVDS3BAR_CLK

LVDS1BAR_CLK

LVDS1_CLK

16 - pin SSOP