PLL520-40

CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3

4. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current (Loaded Outputs)

40

mA

Operating Voltage

2.97

3.63

V

Output Clock Duty Cycle

45

50

55

%

Short Circuit Current

±50

mA

5. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

77.76MHz

2.5

ps

Period jitter peak-to-peak

77.76MHz

18.5

ps

Integrated jitter RMS

Integrated 12 kHz to 20 MHz at

77.76MHz

0.5

ps

6. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

Phase Noise relative

to carrier

77.76MHz

-75

-95

-125

-145

-155

dBc/Hz

Note: Phase Noise at VCON = 0V

7. CMOS Output Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

30

mA

Output drive current

(High Drive)

30

mA

10

mA

Output drive current

(Standard Drive)

10

mA

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns