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PCF8536AT Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCF8536AT Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 51 page  NXP Semiconductors PCF8551 Universal 36 × 4 LCD segment driver • The address pointer is cleared (set to logic 0) • The display and the internal oscillator are disabled • The display registers are set to logic 0 • The bus interface is initialized Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this case, the internal registers are not defined and require a software reset, see Section 7.3.3. Remark: For power-on with a slowly starting power supply, see Section 15.1. 7.3.3 Command: Software_reset The internal registers including the display registers and the address pointer (set to logic 0) of the device are reset by the Software_reset command. Bit Symbol Value Description software reset 0000 0000[2] no reset 7 to 0 SR[7:0][1] 0010 1100 software reset Table 8. Software_reset - software reset command register (address 00h) bit description [1] Software_reset only generates a reset pulse, therefore this register always reads back as 00h. [2] Default value. 7.4 Display data register mapping Segments SEG0 to SEG7 SEG8 to SEG15 SEG16 to SEG23 SEG24 to SEG31 SEG32 to SEG35 Backplanes[1] LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 1:4 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h COM3 content of 13h content of 14h content of 15h content of 16h content of 17h 1:3 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h 1:2 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh static drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h Table 9. Register to segment and backplane mapping [1] See also Section 8.3.1 PCF8551 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 — 3 May 2021 11 / 51 |
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