Preliminary

PLL702-03

Low EMI Peripheral Clock Generator for Notebook PCs

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 10/06/02 Page 3

PIN DESCRIPTIONS

Name

Pin#

Type

Description

VDDOSC

1

P

3.3V power supply for oscillator, analog core and digital circuitry.

XIN

2

I

Crystal input: for 24.576MHz fundamental crystal (CL = 20pF, parallel resonant mode, +/-

20ppm). On-chip load capacitors: no external load capacitors required.

XOUT

3

O

Crystal output.

VSSOSC

4

P

Ground connection.

VSSB1

5

P

Ground connection.

24.576MHz/SST0

6

B

Bi-directional and Tri-Level pin. Upon power-on, the value of SST0 is latched in and used

to select the SST control (see Spread Spectrum selection table 1). Tri level input: M = Do

not connect, 1 = Pull up, 0 = Pull down. After power-up this pin acts as 24.576MHz output

clock.

24.576MHz/SST1

7

B

Bi-directional pin. Upon power-on, the value of SST1 is latched in and used to select the

SST control (see Spread Spectrum selection table 1). Internal pull down defaults SST1 to

0, use external pull-up to set to 1. After power-up this pin acts as 24.576MHz output clock.

VDDB1

8

P

3.3V power supply for 24.576MHz clock.

VDD25M

9

P

3.3V power supply for 25MHz, 8MHz, 12MHz, 24.576MHz.

25MHzx2

10

O

25MHz Ethernet output clock (double drive strength).

VSS25M

11

P

Ground connection.

12MHz/VDD_SEL

12

B

Bi-directional pin. Upon power-on, the value of VDD_SEL is latched in and used to select

the power (see Power Selection table 2 ). Internal pull down defaults SST1 to 0, use

external pull-up to set to 1. After power-up this pin acts as 12MHz output clock.

8MHz

13

O

8MHz output clock (for Keyboard controller).

VSSB2

14

P

Ground connection.

27MHz

15

O

27MHz output. This output can be modulated for low EMI using SST (Spread Spectrum

Technology).

VDDB2

16

P

3.3V power supply for 27MHz, 20MHz, 12MHz, and 24.576MHz.

FUNCTIONAL DESCRIPTION

Tri-level and two-level inputs

In order to reduce pin usage, the PLL702-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =

Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.