Preliminary

PLL502-67

4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 02/20/03 Page 2

FREQUENCY SELECTION TABLE

SEL2

SEL1

SEL0

Selected Multiplier

0

0

0

Reserved

0

0

1

Reserved

0

1

0

Reserved

0

1

1

Fin x 2

1

0

0

Fin / 2

1

0

1

Fin x 4

1

1

0

Fin x 8

1

1

1

No multiplication

Note:

Internal pull-ups default SEL2, SEL1 and SEL0 to ‘1’ if not connected

PIN DESCRIPTIONS

Name

Pin number

Type

Description

XIN

2

I

Crystal in connector.

XOUT

3

I

Crystal out connector.

VCON

6

I

Frequency control input (0.3V to 3.0V)

GND

7,8

P

GND.

CLK1, CLK2

9,10

O

Output signal

CLK3, CLK4

12,13

O

Output signal.

SEL2

4

I

SEL1

5

I

SEL0

14

I

Multiplier selector pins. These pins have an internal pull-up

that will default SEL to ‘1’ when not connected to GND.

VDD

1, 11

P

+3.3V VDD.