SLG47004 datasheet(3/292 Pages) DIALOG

3 / 292 page

Datasheet

10-Mar-2021

CFR0011-120-00

Revision 2.4

3 of 292

SLG47004

GreenPAK Programmable Mixed-Signal Matrix

with In-System Programmability and Advanced Analog Features

Preliminary

10.2 Modes of Operation ..........................................................................................................................................104

10.3 Op Amps Typical Performance ........................................................................................................................108

11 Analog Switch Macrocell ............................................................................................................................................... 154

11.1 Analog Switch General Description ..................................................................................................................154

11.2 Half Bridge Mode .............................................................................................................................................156

11.3 Analog Switches Typical Performance .............................................................................................................157

12 Digital Rheostats and Programmable Trim Block ....................................................................................................... 159

12.1 Potentiometer Mode .........................................................................................................................................161

12.2 Calculating Actual Resistance ..........................................................................................................................161

12.3 Digital Rheostat Value Self-programming into the NVM ..................................................................................162

12.4 Trimming process Using Programmable Trim Block ........................................................................................165

12.5 Using Chopper ACMP ......................................................................................................................................171

13 Programmable Delay/Edge Detector ............................................................................................................................ 177

13.1 Programmable Delay Timing Diagram - Edge Detector Output .......................................................................177

14 Additional Logic Function. Deglitch Filter ................................................................................................................... 178

15 Voltage Reference .......................................................................................................................................................... 179

15.1 Voltage Reference Overview ...........................................................................................................................179

15.2 Vref Selection Table ........................................................................................................................................179

15.3 Vref Block Diagram ..........................................................................................................................................181

15.4 Voltage Reference Typical Performance .........................................................................................................185

16 Clocking .......................................................................................................................................................................... 188

16.1 OSC General Description .................................................................................................................................188

16.2 Oscillator0 (2.048 kHz) .....................................................................................................................................189

16.3 Oscillator1 (2.048 MHz) ...................................................................................................................................190

16.4 Oscillator2 (25 MHz) ........................................................................................................................................191

16.5 CNT/DLY Clock Scheme ..................................................................................................................................191

16.6 External Clocking .............................................................................................................................................192

16.7 Oscillators Power-On Delay .............................................................................................................................193

16.8 Oscillators Accuracy .........................................................................................................................................195

16.9 Oscillators Settling time ....................................................................................................................................197

16.10 Oscillators Current Consumption ..................................................................................................................199

17 Power-On Reset .............................................................................................................................................................. 203

17.1 General Operation ............................................................................................................................................203

17.2 POR Sequence ................................................................................................................................................204

17.3 Macrocells Output States During POR Sequence ...........................................................................................204

18 I2C Serial Communications Macrocell .......................................................................................................................... 207

18.1 I2C Serial Communications Macrocell Overview ..............................................................................................207

18.2 I2C Serial Communications Device Addressing ...............................................................................................207

18.3 I2C Serial General Timing ................................................................................................................................208

18.4 I2C Serial Communications Commands ...........................................................................................................208

18.5 Chip Configuration Data Protection ..................................................................................................................211

18.6 I2C Serial Command Register Map ..................................................................................................................212

18.7 I2C Additional Options ......................................................................................................................................215

19 Non-Volatile Memory ...................................................................................................................................................... 217

19.1 Serial NVM Write Operations ...........................................................................................................................217

19.2 Serial NVM Read Operations ...........................................................................................................................219

19.3 Serial NVM Erase Operations ..........................................................................................................................219

19.4 Acknowledge Polling ........................................................................................................................................220

19.5 Low power standby mode ................................................................................................................................220

19.6 Emulated EEPROM Write Protection ...............................................................................................................220

20 Analog Temperature Sensor ......................................................................................................................................... 222

21 Register Definitions ....................................................................................................................................................... 225

21.1 Register Map ....................................................................................................................................................225

22 Package Top Marking System Definition ..................................................................................................................... 284

22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package ............................................................................284

23 Package Information ...................................................................................................................................................... 285

23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ......................................285

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