SLG47105 datasheet(3/253 Pages) DIALOG

3 / 253 page

Datasheet

31-Aug-2021

CFR0011-120-00

Revision 3.4

3 of 253

SLG47105

GreenPAK Programmable Mixed-Signal Matrix with High

Voltage Features

7.2 Half Bridge mode .................................................................................................................................................56

7.3 Pre-Driver Mode ...................................................................................................................................................57

7.4 Parallel Connection of HV GPO ...........................................................................................................................57

7.5 Protection Circuits ................................................................................................................................................58

7.6 PWM Voltage Control ...........................................................................................................................................59

7.7 High Voltage Outputs Typical Performance .........................................................................................................60

8 Differential Amplifier with Integrator and Comparator ...................................................................................................70

8.1 Differential Amplifier with Integrator Block Diagram .............................................................................................71

8.2 Differential Amplifier Load Regulation ..................................................................................................................71

9 Current Sense Comparator ...............................................................................................................................................73

9.1 Current Sense Comparator0 Block Diagram ........................................................................................................73

9.2 Current Sense Comparator1 Block Diagram ........................................................................................................74

9.3 Current Regulation ...............................................................................................................................................74

9.4 Current Sense Comparator Typical Performance ................................................................................................75

10 Connection Matrix ............................................................................................................................................................77

10.1 Matrix Input Table .............................................................................................................................................78

10.2 Matrix Output Table ............................................................................................................................................80

10.3 Connection Matrix Virtual Inputs ........................................................................................................................82

10.4 Connection Matrix Virtual Outputs .....................................................................................................................83

11 Combination Function Macrocells ..................................................................................................................................84

11.1 2-bit LUT or D Flip-Flop Macrocells ...................................................................................................................84

11.2 2-bit LUT or Programmable Pattern Generator ..................................................................................................87

11.3 3-bit LUT or D Flip-Flop with Set/Reset Macrocells ...........................................................................................89

11.4 3-bit LUT or D Flip-Flop with Set/Reset Macrocell or PWM Chopper ................................................................96

11.5 3-bit LUT or Pipe Delay/Ripple Counter Macrocell .......................................................................................... 103

11.6 4-bit LUT or D Flip-Flop Macrocell ................................................................................................................... 106

12 Multi-Function Macrocells ............................................................................................................................................. 109

12.1 3-bit LUT or DFF/LATCH with 8-bit Counter/Delay Macrocells ........................................................................ 110

12.2 4-bit LUT or DFF/LATCH with 16-bit Counter/Delay Macrocell ........................................................................ 116

12.3 CNT/DLY/FSM Timing Diagrams ..................................................................................................................... 119

12.4 Wake and Sleep Controller .............................................................................................................................. 128

13 Pulse Width Modulator Macrocell (PWM) ..................................................................................................................... 133

13.1 8-bit/7-bit PWM Configurations ........................................................................................................................ 133

13.2 PWM Inputs ...................................................................................................................................................... 133

13.3 PWM Outputs ................................................................................................................................................... 133

13.4 I2C/Matrix/Auto dynamically changeable Duty Cycle and Period ..................................................................... 134

13.5 I2C PWM Duty Cycle read/write ....................................................................................................................... 134

13.6 Flexible OSC-integrated Divider ....................................................................................................................... 134

13.7 Inverted Output option ...................................................................................................................................... 134

13.8 Changeable dead band option for OUT+ and OUT- ........................................................................................134

13.9 Initial PWM value ............................................................................................................................................. 136

13.10 Sync On/Off setting for Power-Down signal ...................................................................................................136

13.11 Regular/Preset Registers Mode ..................................................................................................................... 140

13.12 PWM Continuous/Autostop mode .................................................................................................................. 141

13.13 Internal Oscillator Auto Disable Mode ............................................................................................................ 141

13.14 Phase Correct PWM Mode ............................................................................................................................ 144

13.15 PWM Period Output ....................................................................................................................................... 144

13.16 PWM Block Diagrams .................................................................................................................................... 145

13.17 PWM Register Settings .................................................................................................................................. 146

14 Analog Comparators ..................................................................................................................................................... 150

14.1 ACMP0H Block Diagram .................................................................................................................................. 151

14.2 ACMP1H Block Diagram .................................................................................................................................. 152

14.3 ACMP Typical Performance ............................................................................................................................. 153

15 Programmable Delay/Edge Detector ............................................................................................................................ 156

15.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT ................................................................... 156

16 Additional Logic Function. Deglitch Filter ................................................................................................................... 157

17 Voltage Reference .......................................................................................................................................................... 158

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