DA7283

Ultra-Low Power LRA Haptic Driver with Multiple Input

Triggers and Software-Free Operation

Datasheet

Revision 3.0

30-Jul-2019

CFR0011-120-00

21 of 22

© 2019 Dialog Semiconductor

9

Layout Guidelines

For optimal layout, place the 100 nF capacitor C1 as close to the VDD and the GND_1 pins as

possible. It is also advisable to use solid a ground plane under the device.

The QFN can be routed out on a single layer. It is recommended to connect GND_1 and GND_2 to a

local ground plane on the top layer with a low-impedance via connection to the main ground plane,

see Figure 16.

VIA

VIA

VIA

VIA

VIA TO

VDD

LAYER

VIA TO GND LAYER

SOLID GND

CONNECTION

ON TOP LAYER

100 nF Capacitor

0201 (0603)

GPI_1

GPI_2

VDDIO/

EN

GPI_0

OUTN

GND_2

VDD

OUTP

GND_1

GND_3

GND_4

GND_5

Figure 15: WLCSP Example PCB Layout

VIA

VIA

VIAS TO

GND LAYER

SOLID GND

CONNECTION

ON TOP LAYER

100 nF Capacitor

0603 (1608)

VIA

VIA

nIRQ

SCL

SDA

VDDIO/EN

OUTN

GND_1

GND_2

OUTP

VDD

GPI_2

GPI_1

GPI_0

Figure 16: QFN Example PCB Layout