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Evaluates: MAX14915

MAX14915 Evaluation Kit

Detailed Description of Hardware

The MAX14915EV kit in conjunction with the USB2GPIO#

adapter board provides easy to use and flexible solution

for evaluation of the MAX14915, octal high-side switch

for industrial applications. It allows SPI communication

between the Windows compatible GUI installed on a PC,

and the MAX14915. The USB2GPIO# adapter board is a

plug and play device that is powered from the USB port

and does not require any additional configuration, refer

to the USB2GPIO data sheet

HERE. A USB driver for

the USB2GPIO# board is installed automatically with the

MAX14915 GUI.

The MAX14915EV kit# can be used as a standalone

board connected to the SPI bus using J6 or/and J7

headers, refer to the MAX14915 EV kit schematic. Up to

four EV kits can be connected to the same SPI bus with

selectable address for each board by appropriate J11 and

J12 jumper settings. For full configuration options, refer

to Table 1.

Load for each channel should be connected to the J8

and J9 terminal block. Each channel (switch) can provide

about 1A of current (typ) and can handle either resistive

or inductive load.

On board diagnostics provide VDD status through

VDDOK LED (DS9), communication error via COMERR#

LED (DS18) and a global fault condition via FAULT#

LED (DS19). Per channel output state and per channel

fault conditions are visible via LED matrix, DS1 through

DS8, and DS10 through DS17, correspondently. Other

diagnostics are provided through the SPI interface by

reading the diagnostic registers 0x03 through 0x09.

Table 1. MAX14915 Board Shunt Positions & Settings

*Default configuration

HEADER

SHUNT POSITION

DESCIPTION

J3

1-2*

VLED supplied from VDD.

Open

Use an external VLED source. Apply VLED power between VLED test point

and GND (TP4).

J4

1-2

Select 3.3V logic level (VL=VA).

Open*

Logic voltage (VL) supplied from USB2GPIO board (3.3V).

Use an external source between VL and GND (TP11) if another host controller

is used.

J5

Open*

Internal 3.3V VA regulator enabled.

1-2

Internal VA regulator disabled (REGEN=GND). Use an external VA source

between VA test point and GND (TP4).

J6

1-2

Set address bit A0 = 1.

2-3*

Set address bit A0 = 0.

J7

1-2

Set address bit A1 = 1.

2-3*

Set address bit A1 = 0.