AM79C978AVCW datasheet(101/256 Pages) AMD

101 / 256 page

Am79C978A

101

before

setting

MEMEN.

The

Am79C978A controller will only

respond to accesses to the Ex-

pansion

ROM

when

both

ROMEN (PCI Expansion ROM

Base Address register, bit 0) and

MEMEN are set to 1. Since ME-

MEN also enables the memory

mapped

access

the

Am79C978A I/O resources, the

PCI Memory Mapped I/O Base

Address register must be pro-

grammed with an address so that

the device does not claim cycles

not intended for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

IOEN

I/O Space Access Enable. The

Am79C978A controller will ignore

all I/O accesses when IOEN is

cleared. The host must set IOEN

before the first I/O access to the

device. The PCI I/O Base Ad-

dress

must

pro-

grammed with a valid I/O address

before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains

status information for the PCI bus related events. It is

located at offset 06h in the PCI Configuration Space.

Bit

Name

Description

PERR

Parity Error. PERR is set when

the

Am79C978A

controller

detects a parity error.

The Am79C978A controller sam-

ples the AD[31:0], C/BE[3:0], and

the PAR lines for a parity error at

the following times:

• In slave mode, during the ad-

dress phase of any PCI bus

command.

• In slave mode, for all I/O, mem-

ory, and configuration write com-

mands

that

select

the

Am79C978A

controller

when

data is transferred (TRDY and

IRDY are asserted).

In master mode, during the data

phase

all

memory

read

commands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C978A controller

sets the PERR bit if the target re-

ports a data parity error by

asserting the PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C978A

controller and cleared by writing a

1. Writing a 0 has no effect.

PERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

SERR

Signaled SERR. SERR is set

when the Am79C978A controller

detects an address parity error

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the Am79C978A

controller and cleared by writing a

1. Writing a 0 has no effect.

SERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

RMABORT Received

Master

Abort.

RM-

ABORT

set

when

the

Am79C978A

controller

termi-

nates a master cycle with a mas-

ter abort sequence.

RMABORT

set

the

Am79C978A

controller

and

cleared by writing a 1. Writing a 0

has no effect. RMABORT is

cleared by H_RESET and is not

affected by S_RESET or by

setting the STOP bit.

RTABORT

Received

Target

Abort.

RT-

ABORT is set when a target ter-

minates an Am79C978A master

cycle

with

target

abort

sequence.

AM79C978AVCW Datasheet(PDF) 101 Page - Advanced Micro Devices

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