AM79C978AVCW datasheet(142/256 Pages) AMD

142 / 256 page

142

Am79C978A

or S_RESET and is not affected

by STOP.

7-0

IFS1

InterFrameSpacingPart1. Chang-

ing IFS1 allows the user to pro-

gram the value of the InterFrame-

SpacePart1

timing.

The

Am79C978A controller sets the

default value at 60 bit times (3ch).

See the subsection on Medium

Allocation in the section Media

Access Management for more

details. The equation for setting

IFS1 when IPG

≥ 96 bit times is:

IFS1 = IPG - 36 bit times

Note: Programming of the IPG

should be done in nibble intervals

instead of absolute bit times due

to the MII. The decimal and hex

values do not match due to de-

lays in the part used to make up

the final IPG.

Changes should be added or sub-

tracted from the provided hex val-

ue on a one-for-one basis. Due to

changes in synchronization de-

lays internally through different

network ports, the IFS1 can be off

by as much as +12 bit times.

These bits are read accessible al-

ways. Write accessible only when

the SPND bit or the STOP bit is

set to 1. IFS1 is set to 3ch (60 bit

times)

H_RESET

S_RESET and is not affected by

STOP.

AM79C978AVCW Datasheet(PDF) 142 Page - Advanced Micro Devices

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