AM79C978AVCW datasheet(138/256 Pages) AMD

138 / 256 page

138

Am79C978A

CSR85: DMA Address Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAU

This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address for

sequential operations. The DMA-

BAU register is undefined until the

first Am79C978A controller DMA

operation.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR86: Buffer Byte Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved. Read and written with

ones.

11-0

DMABC

DMA Byte Count Register. Con-

tains the two’s complement of the

current size of the remaining

transmit or receive buffer in bytes.

This register is incremented by the

Bus Interface Unit. The DMABC

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR88: Chip ID Register Lower

Bit

Name

Description

31-28 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

27-12 PARTID

Part number. The 16-bit code for

the

Am79C978A

controller

0010 0110 0010 0110 (2626h).

This register is exactly the same

as the Device ID register in the

JTAG description. However, this

part number is different from that

stored in the Device ID register in

the PCI configuration space.

Read accessible only when ei-

ther the STOP or the SPND bit is

set. PARTID is read only. Write

operations are ignored.

11-1

MANFID

Manufacturer ID. The 11-bit man-

ufacturer

code

for

AMD

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configuration space.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. MANFID is

read only. Write operations are

ignored.

ONE

Always a logic 1.

Read accessible only when ei-

ther the STOP or the SPND bit is

set. VER is read only. ONE is

read only. Write operations are

ignored.

CSR89: Chip ID Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Read as un-

defined.

15-12 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

VER is read only. Write opera-

tions are ignored.

11-0

PARTIDU

Upper 12 bits of the Am79C978A

controller part number, i.e., 0010

0110 0010b (262h).

AM79C978AVCW Datasheet(PDF) 138 Page - Advanced Micro Devices

AM79C978AVCW Datasheet(HTML) 138 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL