AM79C978AVCW datasheet(137/256 Pages) AMD

137 / 256 page

Am79C978A

137

Transmit

FIFO

without

FIFO

overflow. Transmit DMA is re-

quested at any time when the

number of bytes specified by

XMTFW could be written to the

FIFO without causing Transmit

FIFO overflow and the internal

microcode engine has reached a

point where the Transmit FIFO is

checked to determine if DMA

servicing is required.

When

operating

the

NO-

SRAM mode (no SRAM en-

abled) and SRAM_SIZE is set to

0, the Bus Transmit FIFO and

the MAC Transmit FIFO operate

like a single FIFO and the water-

mark value selected by XMT-

FW[1:0] sets the number of FIFO

byte locations that must be avail-

able in the FIFO before receive

DMA is requested.

When operating with the SRAM,

the Bus Transmit FIFO and the

MAC Transmit FIFO operate in-

dependently on the bus side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by XMTFW[1:0] sets the

number of FIFO byte locations

that must be available in the Bus

Transmit FIFO. See Table 35.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. XMTFW is

set to a value of 00b (16 bytes) af-

ter H_RESET or S_RESET and

is unaffected by STOP.

7-0

DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect. Use MAX_LAT and MIN_GNT

in the PCI configuration space.

CSR82: Transmit Descriptor Address Pointer Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

TXDAPL

Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If

the previous transmit frame did

not use buffer chaining, then

TXDAPL contains the lower 16

bits of the

previous frame’s

transmit descriptor address.

When both the STOP or SPND

bits are cleared, this register is up-

dated by the Am79C978A control-

ler immediately before a transmit

descriptor write.

Read accessible always. Write ac-

cessible through the PXDAL bits

(CSR60) when the STOP or SPND

bit is set. TXDAPL is set to 0 by

H_RESET and are unaffected by

S_RESET or STOP.

CSR84: DMA Address Register Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAL

This register contains the low-

er 16 bits of the address of

system memory for the current

DMA cycle. The Bus Interface

Unit controls the Address Reg-

ister

issuing

increment

commands to increment the

memory address for sequential

operations. The DMABAL reg-

ister is undefined until the first

Am79C978A

controller

DMA

operation.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

Table 35.

Transmit Watermark Programming

XMTFW[1:0]

Bytes Available

108

Reserved

AM79C978AVCW Datasheet(PDF) 137 Page - Advanced Micro Devices

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