AM79C978AVCW datasheet(134/256 Pages) AMD

134 / 256 page

134

Am79C978A

CSR64: Next Transmit Buffer Address Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NXBAL

Contains the lower 16 bits of the

next transmit buffer address from

which the Am79C978A controller

will transmit an outgoing frame.

These bits are read/write accessi-

ble only when either the STOP or

the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR65: Next Transmit Buffer Address Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NXBAU

Contains the upper 16 bits of the

next transmit buffer address from

which the Am79C978A controller

will transmit an outgoing frame.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR66: Next Transmit Byte Count

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved locations. Read and

written as zeros.

11-0

NXBC

Next Transmit Byte Count. This field

is a copy of the BCNT field of TMD1

of the next transmit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR67: Next Transmit Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NXST

Next Transmit Status. This field is

a copy of bits 31-16 of TMD1 of

the next transmit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

7-0

RES

Reserved locations. Read and

written as zeros. Accessible only

when either the STOP or the

SPND bit is set.

CSR72: Receive Ring Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCVRC

Receive Ring Counter location.

Contains a two’s complement bi-

nary number used to number the

current receive descriptor. This

counter interprets the value in

CSR76 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR74: Transmit Ring Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

XMTRC

Transmit Ring Counter location.

Contains a two’s complement bi-

nary number used to number the

current transmit descriptor. This

counter interprets the value in

CSR78 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

AM79C978AVCW Datasheet(PDF) 134 Page - Advanced Micro Devices

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