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AM79C978AVCW Datasheet(PDF) 133 Page - Advanced Micro Devices

Part # AM79C978AVCW
Description  Single-Chip 1/10 Mbps PCI Home Networking Controller
PDF  256 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C978AVCW Datasheet(HTML) 133 Page - Advanced Micro Devices

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Am79C978A
133
CSR60: Previous THd3nsmit Descriptor Address
Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PXDAL
Contains the lower 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978A
controller has the capability to
stack multiple transmit frames.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR61: Previous Transmit Descriptor Address
Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PXDAU
Contains the upper 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978A
controller has the capability to
stack multiple transmit frames.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR62: Previous Transmit Byte Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations.
11-0
PXBC
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR63: Previous Transmit Status
Bit
NameDescription
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PXST
Previous Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the previous transmit
descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Table 32.
Software Styles
SWSTYLE
[7:0]
Style
Name
SSIZE32
Initialization Block
Entries
Descriptor Ring Entries
00h
LANCE/PCnet-ISA
controller
0
16-bit software structures,
non-burst or burst access
16-bit software structures,
non-burst access only
01h
RES
1
RES
RES
02h
PCnet-PCI
controller
1
32-bit software structures,
non-burst or burst access
32-bit software structures,
non-burst access only
03h
PCnet-PCI
controller
1
32-bit software structures,
non-burst or burst access
32-bit software structures,
non-burst or burst access
All Other
RES
Undefined
Undefined
Undefined



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