MDS 558-02 D

2

Revision 020504

ICS558-02

Pin Assignment

Tri-State Table

Output Divide Selection

Pin Descriptions

12

1

11

2

10

3

9

SEL

4

VDD

5

VDD

6

VDD

7

HCLK

8

HCLK

CLK1

CLK2

CLK3

GND

CLK4

OE1

GND

GND

16

15

14

13

OE0

VDD

16 Pin 173 Mil (0.65mm) TSSOP

OE1

OE0

CLK 1, CLK 2

CLK 3, CLK 4

00

Tri-state

Tri-state

0

1

Clock ON

Tri-state

1

0

Tri-state

Clock ON

1

1

Clock ON

Clock ON

SEL

Output Divide

0/3

1/4

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

SEL

Input

Select pin for output divider. See table above. Internal pull-up to VDD.

2

VDD

Power

Connect to +3.3 V.

3

VDD

Power

Connect to +3.3 V.

4

HCLK

Input

Differential LVHSTL input (true input).

5

HCLK

Input

Differential LVHSTL input (complimentary input).

6

GND

Power

Connect to ground.

7

GND

Power

Connect to ground.

8

OE0

Input

Output enable for CLK1 and CLK2. See table above. Internal pull-up

to VDD.

9

OE1

Input

Output enable for CLK3 and CLK4. See table above. Internal pull-up

to VDD.

10

GND

Power

Connect to ground.

11

CLK4

Output

Low skew clock output.

12

CLK3

Output

Low skew clock output.

13

CLK2

Output

Low skew clock output.

14

CLK1

Output

Low skew clock output.

15

VDD

Power

Connect to +3.3 V.

16

VDD

Power

Connect to +3.3 V.