USB7252CTSLASHKDX datasheet(43/63 Pages) MICROCHIP

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2021 Microchip Technology Inc.

DS00003852A-page 43

• Disable SPI Pass-Through Interface

For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging

with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7252C product page at

www.microchip.com/USB7252C.

8.10 USB to UART Bridging

The USB to UART bridging feature provides system designers with expanded system control and potential BOM reduc-

tion. When using Microchip’s USB hubs, a separate USB to UART device is no longer required and a downstream USB

port is not lost, as occurs when a standalone USB to UART device is implemented.

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-

form the following functions:

• Enable/Disable UART Interface

• Set UART Interface Baud Rate

• UART Write

• UART Read

For detailed information on utilizing the USB to UART bridging feature, refer to the application note “USB to UART Bridg-

ing with Microchip USB7202 and USB725x Hubs”, which can be found on the Microchip USB7252C product page at

www.microchip.com/USB7252C.

8.11 Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM

states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB

suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.

8.12 Resets

The device includes the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.12.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On

and Configuration Strap Timing.

TABLE 8-1:

LPM STATE DEFINITIONS

State

Description

Entry/Exit Time to L0

Suspend

Entry: ~3 ms

Exit: ~2 ms (from start of RESUME)

Sleep

Entry: <10 us

Exit: <50 us

Fully Enabled (On)

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