Integrated

Circuit

Systems, Inc.

840004AGI-01

www.icst.com/products/hiperclocks.html

REV. A JUNE 28, 2005

8

ICS840004I-01

PRELIMINARY

The transistor count for ICS840004I-01 is: TBD

θ

JA

VS

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

98.0°C/W

88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Figure 3 shows a schematic example of the ICS840004I-01. An

example of LVCMOS termination is shown in this schematic.

Additional LVCMOS termination approaches are shown in the

LVCMOS Termination Application Note. In this example, an 18pF

parallel resonant 25MHz crystal is used. The C1=22pF and

C2=22pF are recommended for frequency accuracy. For differ-

ent board layout, the C1 and C2 may be slightly adjusted for

optimizing frequency accuracy. 1K

Ω pullup or pulldown resis-

tors can be used for the logic control input pins.

XTAL_IN

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

RU1

1K

LVCMOS

VDDO=3.3V

R4

100

R3

36

Logic Control Input Examples

VDDA

C5

0.1u

VDD=3.3V

RD1

Not Install

VDD

X1

C3

10uF

To Logic

Input

pins

Optional Termination

VDD

Set Logic

Input to

'1'

R5

100

U1

ICS840004i-01

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

F_SEL0

nc

nXTAL_SEL

TEST_CLK

OE

MR

nPLL_SEL

VDDA

nc

VDD

XTAL_OUT

XTAL_IN

GND

Q3

Q2

VDDO

F_SEL1

GND

Q0

Q1

C2

22pF

C6

0.1u

VDDO

RU2

Not Install

LVCMOS

R2

10

Zo = 50 Ohm

VDD

VDD

VDD

RD2

1K

VDD

Set Logic

Input to

'0'

XTAL_OUT

C1

22pF

To Logic

Input

pins

If not using the crystal input, it can be left floating.

For additional protection the XTAL_IN pin can be

tied to ground.

C4

0.01u

Zo = 50 Ohm