MAX32010 Evaluation Kit

Evaluates: MAX32010

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1)

MAX32010 Settings: The MAX32010 can be quickly configured through control register settings. An 18-bit word

programs the MAX32010.

The Measurement Mode group box is a quick way to set the MAX32010 to force voltage (FV), force current (FI),

force current as a slave device (FI Slave), or place into high impedance (Hi-Z). Bit settings are automatically changed

to match the mode settings as follows:

•

In Hi-Z mode, all the bits in control register are unchecked.

•

In FI Slave mode, FMODE bit is checked and all other bits are unchecked.

•

In FV mode,

bit is set and all other bits are unchecked.

•

In FI mode, both

and FMODE bits are set and all other bits are unchecked.

The Measurement Mode group box provides the measured voltages at IMEAS and VMEAS pins of the MAX32010.

Table 1 shows the settings and functionality of these bits in the GUI:

Table 1. Settings and Functions of the GUI Bits

SETTING

FUNCTION

VGA Gain

This horizontal scrollbar controls the gain and polarity of the variable gain amplifiers (VGA).

Range

This horizontal scrollbar controls the full-scale current range for either FI (force current)

or MI (measure current) mode.

FMODE

This checkbox selects DPS mode (FV, FI, FI slave, and high impedance).

CLEN

This checkbox enables or disables the voltage and current clamps.

This checkbox along with FMODE selects DPS mode (FV, FI, FI slave, and high impedance).

This checkbox controls the measure output’s high-impedance state.

This checkbox controls t

he comparator output’s high-impedance state.

LCOMP1 and LCOMP0

These checkboxes enable or disable compensation capacitors.

BCOMP1 and BCOMP0

These checkboxes enable or disable bypass capacitors.

2)

MAX32010 Signals and Data Flow Control: HIZMPB and IDDQSEL are signals that can be used to control the

functionality of the MAX32010. The HIZMPB signal is shared in functionality with the HIZMSB bit and internally both

bits are ANDed. It is used either to enable the measurement output or to put the measurement output in the high-

impedance state. While in FV mode asserting digital input, IDDQSEL switches the DPS to the minimum current range

(range D) and enabling the IDDQ test mode.

Data flow control bits specify how data transfers from the shift registers to the input and DPS register of the

MAX32010. Refer to Serial Interface Data Flow Control Bits section in the MAX32010 data sheet for more details.

Table 2 shows the options available for controlling the data flow:

Table 2. Data Flow Control Settings

SETTING

DESCRIPTION

00

Input and DPS registers remain unchanged

01

DPS registers get loaded from input register

10

Input registers get loaded from shift register

11

Both DPS and input registers get loaded from shift register