PCF8536AT datasheet(5/50 Pages) NXP

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NXP Semiconductors

PCA8561

Automotive 18 × 4 LCD segment driver

6.2 Pin description

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Type

Description

COM3

output

LCD backplane output

VLCD

supply

LCD supply voltage

VDD

supply

supply voltage

VSS[1]

supply

ground supply

RST

input

reset input, active LOW

CLK

input/output

internal oscillator output, external oscillator input

• must be left open if unused

SCL

input

serial clock input

PORE[2]

input

Power-On Reset (POR) enable

• connect to VDD for enabling POR

• connect to VSS (or leave open) for disabling POR

12 to 29 SEG0 to SEG17

output

LCD segment outputs

30 to 32 COM0 to COM2

output

LCD backplane outputs

Pin layout depending on product and bus type

PCA8561AHN

(I2C-bus)

PCA8561BHN

(SPI-bus)

A0[2]

input

hardware device address selection;

• connect to VSS (or leave open) for logic 0

• connect to VDD for logic 1

SDIO

input/output

serial data input/output

SDA

output

serial data output

input

chip enable input, active LOW

A1[2]

input

hardware device address selection;

• connect to VSS (or leave open) for logic 0

• connect to VDD for logic 1

n.c.

not connected

Table 3. Pin description

[1]

The die paddle (exposed pad) is connected to VSS and should be electrically isolated.

[2]

A series resistance between VDD and the pin must not exceed 1 kΩ to ensure proper functionality, see Section 15.3.

PCA8561

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 March 2021

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