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ICS843034AY Datasheet(PDF) 18 Page - Integrated Circuit Systems |
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ICS843034AY Datasheet(HTML) 18 Page - Integrated Circuit Systems |
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18 / 23 page  843034AY www.icst.com/products/hiperclocks.html REV. A JULY 25, 2005 18 Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY APPLICATION SCHEMATIC EXAMPLE Figure 8 shows a schematic example of using an ICS843034. In this example, the CLK/nCLK input is driven by a 3.3V LVPECL driver. The data sheet also shows the CLK/nCLK input driven by various types of drivers. The crystal inputs are parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are 22pF. This schematic example shows hardwired logic control input handling. The logic inputs can also be driven by 3.3V LVCMOS drivers. It is recommended to have one decouple capacitor per power pin. In general, the decoupling capacitor values are ranged from 0.01uF to 0.1uF. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R9, C11 and C16 for clean analog supply 3. 3V Zo = 50 Ohm Zo = 50 Set Logic Input to '0' C2 22p To Logic Input pins VCCO_REF Alternative Termination Exmaple VCCO_REF=3.3V VCC LVCMOS VCCA C8 0.1u C9 0. 1u R8 43 R11 50 R12 50 C11 0.01u R3 50 VCC X1 CL=18pF R1 50 C3 22p Set Logic Input to '1' R7 82.5 RD2 1K R4 133 RU2 SPARE C4 22p VCC R9 10 C6 0.1u R2 50 R10 50 C1 22p C7 0.1u + - Zo = 50 Ohm Zo = 50 Ohm VCCO=3.3V Zo = 50 Ohm Logic Input Pin Examples Zo = 50 Ohm + - VCC VCCO VCC RD1 SPARE RU1 1K LVPECL VCC=3.3V C5 0.1u R5 82.5 U1 I CS843034 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE X_OUT1 X_IN1 X_OUT0 X_IN0 TEST_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR Zo = 50 C16 10u R6 133 To Logic Input pins VCCO X1 CL=18pF FIGURE 8. ICS843034 APPLICATION SCHEMATIC EXAMPLE should also be located as close to the VCCA pin as possible. Only two examples of 3.3V LVPECL termination are shown in this schematic example. Additional LVPECL terminations can be found in the LVPECL Termination Application Note. The data sheet also shows 2.5V LVPECL terminations. The REF_CLK is LVCMOS driver with 7 Ω output impedance. Series termination for REF_CLK is shown in the example. Additional LVCMOS termination can be found in the LVCMOS Application Note. If the REF_CLK is not used, it is recommended to disable this output by setting REF_OE to logic low. To disable REF_CLK, REF_OE pin can be left floating (default logic low by internal 51K pull down) or pull down using an external 1K Ω resistor. |
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