LTC4451

9

Rev. 0

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APPLICATIONS INFORMATION

coupling onto the SHDN# pin is a concern, a capacitor to

ground can be included.

Input Short-Circuit Faults

The dynamic behavior of an active LTC4451 ideal diode

entering reverse bias mode is most accurately character-

ized by a delay followed by a period of reverse recovery.

During the delay phase, when the gate driver is disabling

the internal N-Channel MOSFET, a reverse current is

present from OUT to IN. The magnitude of this current

depends on the timing of the part, reverse voltage and

parasitic impedances along the power path. After reverse

recovery, energy stored in the parasitic inductances is

transferred to other elements in the circuit, resulting in

high current transients and potentially destructive volt-

age spikes.

High slew rates coupled with parasitic inductances in

series with the input and output paths may cause poten-

tially destructive transients to appear at the IN and OUT

pins of the LTC4451 during reverse recovery.

A zero impedance short-circuit directly across the input

and ground is especially troublesome because it permits

the highest possible reverse current to build up during

the delay phase. When the internal MOSFET turns off to

interrupt the reverse current, the LTC4451 IN pin experi-

ences a negative voltage spike while the OUT pin spikes

in the positive direction.

To prevent damage to the LTC4451 under conditions of an

input short-circuit, protect the IN and OUT pins as shown

in Figure 3. The IN pin is protected by clamping to the

GND pin with a Schottky diode. Negative spikes, seen after

the MOSFET turns off during an input short are clamped

and protect the LTC4451. When the input short condition

disappears, the current stored in the parasitic inductance,

IN and OUT pins may rise to a level that can damage the

LTC4451. In this case, D1 needs to be a TransZorb or

TVS to limit the voltage difference between the IN and

GND pins.

OUT is protected by the MOSFET’s avalanche breakdown

damaged by excessive current in higher voltage applica-

tions. A TVS (D2) can be used to protect the MOSFET

when output parasitic inductance causes the IN and OUT

voltages to drop quickly.

Layout Considerations

High current applications demand careful attention to

trace resistances. The PCB trace associated with the IN/

OUT pins should have low resistance to reduce conduc-

tion power loss. Keep the traces to the IN and OUT pins

Figure 3. Input Short Protection Circuit with Parasitic Inductances

SW

D2

(OPTIONAL)

D1

CDBA20

1A

40V

LTC4451

GND

OUT

IN

INPUT

SHORT

SWITCH

INPUT PARASITIC

INDUCTANCE

OUTPUT PARASITIC

INDUCTANCE

REVERSE

RECOVERY CURRENT

SOURCE PARASITIC

INDUCTANCE

4451 F03

+

–

+

–

+

–

0.1µF