ICS844071I datasheet(7/10 Pages) ICST

7 / 10 page

844071AGI

www.icst.com/products/hiperclocks.html

REV. A JULY 13, 2005

Integrated

Circuit

Systems, Inc.

ICS844071I

FEMTOCLOCKS™CRYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in

Figure 3. In a 100

differential transmission line environment, LVDS drivers

require a matched load termination of 100

Ω across near

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

2.5V or 3.3V

VDD

100 Ohm Differential Transmission Line

100

LVDS_Driv er

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS844071I has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

The optimum C1 and C2 values can be slightly adjusted for dif-

ferent board layouts.

22p

18pF Parallel Crystal

33p

XTAL_OUT

XTAL_IN

ICS844071I Datasheet(PDF) 7 Page - Integrated Circuit Systems