ICS16859C datasheet(1/8 Pages) ICST

Part #	ICS16859C

Description	DDR 13-Bit to 26-Bit Registered Buffer

PDF	8 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 8 page

Integrated

Circuit

Systems, Inc.

ICSSSTV16859C

0703A—10/15/02

Recommended Applications:

• DDR Memory Modules

• Provides complete DDR DIMM logic solution with

ICS93V857 or ICS95V857

• SSTL_2 compatible data registers

Product Features:

• Differential clock signals

• Meets SSTL_2 signal data

• Supports SSTL_2 class II specifications on outputs

• Low-voltage operation

- VDD = 2.3V to 2.7V

• Available in 64 pin TSSOP and 56 pin VFQFN (MLF2)

packages

DDR 13-Bit to 26-Bit Registered Buffer

Truth Table

1

Block Diagram

Notes:

1.

H = "High" Signal Level

L = "Low" Signal Level

↑ = Transition "Low"-to-"High"

↓ = Transition "High"-to-"Low"

X = Don't Care

2.

Output level before the indicated steady state

input conditions were established.

s

t

u

p

n

Is

t

u

p

t

u

O

Q

#

T

E

S

E

RK

L

C#

K

L

CD

Q

L

r

o

X

g

n

i

t

a

o

l

F

r

o

X

g

n

i

t

a

o

l

F

r

o

X

g

n

i

t

a

o

l

F

L

H

↑↓

HH

H

↑↓

LL

HH

r

o

LH

r

o

LX

Q0 )

2

(

56-Pin VFQFN (MLF2)

Pin Configurations

64-Pin TSSOP

6.10 mm. Body, 0.50 mm. pitch

Q7A

Q6A

Q5A

Q4A

Q3A

Q2A

Q1A

Q13B

VDDQ

Q12B

Q11B

Q10B

Q9B

Q8B

1

14

15

28

29

43

42

56

D10

D9

D8

D7

RESET#

GND

CLK#

CLK

VDDQ

VDD

VREF

D6

D5

D4

ICSSSTV16859C

CLK

CLK#

D1

VREF

RESET#

To 12 Other Channels

Q1A

Q1B

CLK

R

D1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Q13A

Q12A

Q11A

Q10A

Q9A

VDDQ

GND

Q8A

Q7A

Q6A

Q5A

Q4A

Q3A

Q2A

GND

Q1A

Q13B

VDDQ

Q12B

Q11B

Q10B

Q9B

Q8B

Q7B

Q6B

GND

VDDQ

Q5B

Q4B

Q3B

Q2B

Q1B

VDDQ

GND

D13

D12

VDD

VDDQ

GND

D11

D10

D9

GND

D8

D7

RESET#

GND

CLK#

CLK

VDDQ

VDD

VREF

D6

GND

D5

D4

D3

GND

VDDQ

VDD

D2

D1

GND

VDDQ

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