ICS8421002AI datasheet(8/13 Pages) ICST

8 / 13 page

8421002AGI

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 7, 2006

Integrated

Circuit

Systems, Inc.

ICS8421002I

FEMTOCLOCKS™CRYSTAL-TO-

HSTL FREQUENCY SYNTHESIZER

CRYSTAL INPUT INTERFACE

The ICS8421002I has been characterized with 18pF parallel

resonant crystals. The capacitor values shown in Figure 2

Figure 2. CRYSTAL INPUt INTERFACE

below were determined using a 26.5625MHz 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

ICS8421002I

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8421002I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD, VDDA, and VDDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each V

DDA.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

DDA

μF

.01

μF

3.3V or 2.5V

.01

μF

22p

18pF Parallel Crystal

22p

XTAL_OUT

XTAL_IN

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

resistor can be tied from XTAL_IN to ground.

REF_CLK INPUT:

For applications not requiring the use of the reference clock,

it can be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the REF_CLK to

ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

HSTL OUTPUT

All unused HSTL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

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