MAX17271 datasheet(21/37 Pages) MAXIM

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I2C Interface Power

The MAX17231’s I2C interface derives its power from

VIO. Typically a power input such as VIO would require

a local 0.1μF ceramic bypass capacitor to ground.

However, in highly integrated power distribution systems,

a dedicated capacitor might not be necessary. If the

impedance between VIO and the next closest capacitor

(≥ 0.1μF) is less than 100mΩ in series with 10nH, then a

local capacitor is not needed. Otherwise, bypass VIO to

GND with a 0.1µF ceramic capacitor.

VIO accepts voltages from 1.7V to 3.6V (VIO). Cycling VIO

does not reset the I2C registers. When VIN is less than

VUVLO, SDA and SCL are high impedance.

I2C Data Transfer

One data bit is transferred during each SCL clock cycle.

The data on SDA must remain stable during the high

period of the SCL clock pulse. Changes in SDA while SCL

is high are control signals. See the I2C Start and Stop

Conditions section. Each transmit sequence is framed by

a START (S) condition and a STOP (P) condition. Each

data packet is nine bits long: eight bits of data followed by

the acknowledge bit. Data is transferred with the MSB first.

I2C Start and Stop Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issuing

a START condition. A START condition is a high-to-low

transition on SDA with SCL high. A STOP condition is a low-

to-high transition on SDA, while SCL is high. See Figure 5.

A START condition from the master signals the

beginning of a transmission to the MAX17271. The

master terminates transmission by issuing a not-acknowl-

edge followed by a STOP condition (see I2C Acknowledge

Bit for information on not-acknowledge). The STOP

condition frees the bus. To issue a series of commands

to the slave, the master can issue repeated start (Sr)

commands instead of a STOP command to maintain

control of the bus. In general a repeated start command is

functionally equivalent to a regular start command.

When a STOP condition or incorrect address is detected,

the MAX17271 internally disconnect SCL from the serial

interface until the next START condition, minimizing digital

noise and feedthrough.

I2C Acknowledge Bit

Both the I2C bus master and the MAX17271 (slave)

generate acknowledge bits when receiving data. The

acknowledge bit is the last bit of each nine bit data packet.

To generate an acknowledge (A), the receiving device

must pull SDA low before the rising edge of the acknowl-

edge-related clock pulse (ninth pulse) and keep it low

during the high period of the clock pulse. See Figure 6.

To generate a not-acknowledge (nA), the receiving device

allows SDA to be pulled high before the rising edge of the

acknowledge-related clock pulse and leaves it high during

the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection

of unsuccessful data transfers. An unsuccessful data

transfer occurs if a receiving device is busy or if a system

fault has occurred. In the event of an unsuccessful data

transfer, the bus master should reattempt communication

at a later time.

The MAX17271 issues an ACK for all register

addresses in the possible address space even if the

particular register does not exist.

Figure 5. I2C Start and Stop Conditions

Figure 6. Acknowledge Bit

SCL

SDA

tHD;STA

tSU;STA

tSU;STO

tHD;STA

TSU;DAT

SCL

SDA

THD;DAT

NOT ACKNOWLEDGE (NA)

ACKNOWLEDGE (A)

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