MCIMX6DP4AVT2AB datasheet(98/160 Pages) NXP

98 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

NOTE

Table 60 provides information for both the DISP0 and DISP1 ports.

However, DISP1 port has reduced pinout depending on IOMUXC

configuration and therefore may not support all configurations. See the

IOMUXC table for details.

4.12.10.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls.

4.12.10.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control

has a permanent period and a permanent waveform.

IPUx_DIx_PIN04

—

Additional frame/row synchronous

signals with programmable timing

IPUx_DIx_PIN05

—

IPUx_DIx_PIN06

—

IPUx_DIx_PIN07

—

IPUx_DIx_PIN08

—

IPUx_DIx_D0_CS

—

IPUx_DIx_D1_CS

—

Alternate mode of PWM output for

contrast or brightness control

IPUx_DIx_PIN11

—

IPUx_DIx_PIN12

—

IPUx_DIx_PIN13

—

IPUx_DIx_PIN14

—

Optional RS2

IPUx_DIx_PIN15

DRDY/DV

Data validation/blank, data enable

IPUx_DIx_PIN16

—

Additional data synchronous

signals with programmable

features/timing

IPUx_DIx_PIN17

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.

• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.

3 This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

Table 60. Video Signal Cross-Reference (continued)

i.MX

6DualPlus/6QuadPlus

LCD

Comment1,2

Port Name

(x = 0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb3

16-bit

YCrCb

20-bit

YCrCb

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