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AT90USB646 Datasheet(PDF) 129 Page - ATMEL Corporation

Part # AT90USB646
Description  Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
PDF  434 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90USB646 Datasheet(HTML) 129 Page - ATMEL Corporation

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7593A–AVR–02/06
AT90USB64/128
Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified
schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the
OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.
Figure 14-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 14-1, Table 14-2 and Table 14-3 for
details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the out-
put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 118.
The COMnx1:0 bits have no effect on the Input Capture unit.
14.7.1
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 14-1 on page 141. For fast PWM mode refer to Table 14-2 on
page 141, and for phase correct and phase and frequency correct PWM refer to Table 14-3 on
page 142.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
FOCnx
clk
I/O



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