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AT90USB646 Datasheet(PDF) 49 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 434 page  49 7593A–AVR–02/06 AT90USB64/128 6.11 PLL The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1). 6.11.1 Internal PLL for USB interface The internal PLL in AT90USB64/128 generates a clock frequency that is 24x multiplied from nominally 2 MHz input. The source of the 2 MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 2 MHz (See Section 6.11.2 for PLL interface). Table 6-12. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved |
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