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AT90USB646 Datasheet(PDF) 146 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 146 Page - ATMEL Corporation |
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146 / 434 page  146 7593A–AVR–02/06 AT90USB64/128 14.10.8 Timer/Counter3 – TCNT3H and TCNT3L The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 120. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com- pare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. 14.10.9 Output Compare Register 1 A – OCR1AH and OCR1AL 14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL 14.10.11 Output Compare Register 1 C – OCR1CH and OCR1CL 14.10.12 Output Compare Register 3 A – OCR3AH and OCR3AL TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 OCR1C[15:8] OCR1CH OCR1C[7:0] OCR1CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 OCR3A[15:8] OCR3AH OCR3A[7:0] OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 00 0 0 |
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