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AT90USB646 Datasheet(PDF) 228 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 228 Page - ATMEL Corporation |
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228 / 434 page ![]() 228 7593A–AVR–02/06 AT90USB64/128 The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. • Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 20.6.6 TWI (Slave) Address Mask Register – TWAMR • Bits 7..1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 20-10 shows the address match logic in detail. Figure 20-10. TWI Address Match Logic, Block Diagram • Bit 0 – Res: Reserved Bit This bit is reserved and will always read as zero. 20.7 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should gener- ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus. When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current Bit 765 4321 0 TWAM[6:0] – TWAMR Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 000 0000 0 Address Match Address Bit Comparator 0 Address Bit Comparator 6..1 TWAR0 TWAMR0 Address Bit 0 |
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