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AT90USB646 Datasheet(PDF) 347 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 347 Page - ATMEL Corporation |
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347 / 434 page  347 7593A–AVR–02/06 AT90USB64/128 Figure 27-4. General Port Pin Schematic Diagram 27.6.2 Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 27-5 is inserted for the 5V reset signal. Figure 27-5. Observe-only Cell CLK RPx RRx WRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE CLK : I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q Q D Q Q D CLR PORTxn Q Q D CLR DDxn PINxn SLEEP SLEEP: SLEEP CONTROL Pxn I/O I/O See Boundary-scan Description for Details! PUExn OCxn ODxn IDxn PUExn: PULLUP ENABLE for pin Pxn OCxn: OUTPUT CONTROL for pin Pxn ODxn: OUTPUT DATA to pin Pxn IDxn: INPUT DATA from pin Pxn 0 1 DQ From Previous Cell ClockDR ShiftDR To Next Cell From System Pin To System Logic FF1 |
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