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AT90USB646 Datasheet(PDF) 358 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 358 Page - ATMEL Corporation |
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358 / 434 page  358 7593A–AVR–02/06 AT90USB64/128 Figure 28-3. Boot Process Description 28.5.4 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Boot Loader operations. • Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared. • Bit 6 – RWWSB: Read-While-Write Section Busy When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi- ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. • Bit 5 – SIGRD: Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” on page 363 for details. An SPM instruction within four cycles HWBE BOOTRST ? Ext. Hardware Conditions ? Reset Vector = Application Reset Reset Vector =Boot Lhoader Reset ? RESET ALE/HWB t SHRH t HHRH Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR Read/Write R/W R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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